The escalating requirements for increased densification and performance in ultra-large scale integration semiconductor wiring require responsive changes in various aspects of semiconductor manufacturing. Conventional practices employed in the manufacture of semiconductor devices, such as bulk silicon CMOS devices, confront various fundamental performance and reliability limitations, particularly in scaling down the size of devices. These limitations include high junction capacitance, ineffective isolation and latch-up sensitivity. High junction capacitance is primarily attributed to high doping levels required to prevent transistor punch-through and parasitic leakage or field turn on. Scale down LOCOS techniques reduces the effective spacings separating adjacent active regions in a semiconductor substrate and, thereby, increases transistor cross-talk and/or latch-up problems. In order to overcome these problems, conventional practices involve the use of larger than minimum isolation spacings and areas, which is inconsistent with the requirements for high densification. Other conventional approaches comprise the use of inefficient guard ring/bar structures which also increases the die size. An increase in die size requires longer interconnects and, hence, results in products with reduced integrated circuit speeds, i.e., greater resistance capacitance (RC) delays.
A conventional alternative design to avoid the disadvantages of the LOCOS techniques, or modified LOCOS techniques, comprises trench isolation. Advantages of trench isolation include improved latch up and field turn on. However, trench isolation is attendant upon various problems, such as I-V kinks, sidewall leakages, low gate oxide breakdowns, and require significantly more complicated manufacturing steps. In order to overcome trench induced sidewall leakages, higher doping is normally introduced along trench sidewalls. Such high doping increases the junction capacitance. The disadvantageous unreliability and performance attributed to the gate oxide and junction capacitance, respectively, render trench isolation unsatisfactory for high volume production.
Another conventional approach is known as silicon-on-insulator (SOI) structures, wherein, a buried oxide region is provided under the surface semiconductor substrate in the active region. SOI structures advantageously provide lower junction capacitance, improved isolation and improved latch up. However, SOI structures suffer from various problems, such as a high number of defects, I-V kinks due to lattice heating, high source/drain resistance and random threshold voltage behavior.
Thus, there exists a need for a semiconductor device having an improved isolation structure. There is further a need for a method of forming an improved isolation structure which is simplified, efficient, cost-effective, and which can be integrated in conventional MOSFET processing. Thus, there exists a need to provide an isolation structure which can be integrated into conventional MOS structures and offer the selective advantages of both the bulk CMOS structure and the SOI structure without their attendant disadvantages. The resulting semiconductor device having such an improved isolation structure would exhibit higher operating speeds, and improved signal-to-noise ratio, linearity, efficiency and wear resistance.